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Integrated Circuit Systems, Inc.
ICS950805
Frequency Generator with 200MHz Differential CPU Clocks
Recommended Application: CK-408 clock for Almador-M and Brookdale-Mobile chipsets. Programmable for group to group skew. Output Features: * 3 Differential CPU Clock Pairs (differential current mode) * 7 PCI (3.3V) @ 33.3MHz * 3 PCI_F (3.3V) @ 33.3MHz * 1 USB (3.3V) @ 48MHz * 1 DOT (3.3V) @ 48MHz * 1 REF (3.3V) @ 14.318MHz * 1 3V66 (3.3V) @ 66.6MHz * 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz * 3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN or 66.6MHz * 1 66MHz_IN/3V66 (3.3V) @ Input/66MHz Features: * Almador Chipset has a DLL driving the clock buffer path for the 3 buffer path 66.6 MHz outputs, 66Buf(0:2). Almador board level designs MUST use pin 22, 66Buf_1, as the feedback connection from the clock buffer path to the Almador (GMCH) chipset. * Supports spread spectrum modulation, down spread 0 to -0.5%. * Efficient power management scheme through PD#, CPU_STOP# and PCI_STOP#. Key Specifications: * CPU Output Jitter <150ps * 3V66 Output Jitter <250ps * 66MHz Output Jitter (Buffered Mode Only) <100ps * CPU Output Skew <100ps
Pin Configuration
VDDREF X1 X2 GND PCICLK_F0 PCICLK_F1 PCICLK_F2 VDDPCI GND PCICLK0 PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK6 VDD3V66 GND 66MHz_OUT0/3V66_2 66MHz_OUT1/3V66_3 66MHz_OUT2/3V66_4 66MHz_IN/3V66_5 *PD# VDDA GND Vtt_PWRGD# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF FS1 FS0 CPU_STOP#* CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 GND VDDCPU CPUCLKT2 CPUCLKC2 MULTSEL0* I REF GND FS2 48MHz_USB 48MHz_DOT VDD48 GND 3V66_1/VCH_CLK PCI_STOP#* 3V66_0 VDD3V66 GND SCLK SDATA
56-Pin 300mil SSOP 6.10 mm. Body, 0.50 mm. pitch TSSOP
* These inputs have 150K internal pull-up resistor to VDD.
Block Diagram
PLL2 48MHz_USB 48MHz_DOT X1 X2 XTAL OSC
Functionality
FS2 FS1 FS0 0 0
3V66_5/66MHz_IN 3V66_3/66MHz_OUT1 3V66_(4,2)/66MHz_OUT(2,0)
CPU (MHz) 66.66 100.00 200.00 133.33 66.66 100.00 200.00 133.33 Tristate TCLK/2
HzOut( 3V66(1:0) 66MV66(4:22:0) 3 ) (MHz) (MHz) 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 Tristate TCLK/4 66.66 66.66 66.66 66.66 66MHz_IN 66MHz_IN 66MHz_IN 66MHz_IN Tristate TCLK/4 Reser ved Reser ved
ICS950805
PCI_F PCI (MHz) 33.33 33.33 33.33 33.33 66MHz_IN/2 66MHz_IN/2 66MHz_IN/2 66MHz_IN/2 Tristate TCLK/8 Reser ved Reser ved
66MHzIn 3V66(5) (MHz) 66.66 66.66 66.66 66.66 66MHz_IN 66MHz_IN 66MHz_IN 66MHz_IN Tristate TCLK/4 Reser ved Reser ved
0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1
0 0 1 1 1 1 Mid Mid Mid Mid
PLL1 Spread Spectrum
REF
CPU DIVDER Stop
3 3
CPUCLKT (2:0) CPUCLKC (2:0) PCICLK (6:0) PCICLK_F (2:0) 66MHz_0
PD# CPU_STOP# PCI_STOP# MULTSEL0 FS (2:0) SDATA SCLK
PCI DIVDER
Stop
7 3
Control Logic
3V66 DIVDER
Reser ved Reser ved Reser ved Reser ved
Config. Reg.
3V66_1/VCH_CLK I REF
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Pin Configuration
PIN NUMBER
1, 8, 14, 19, 26, 32, 37, 46, 50 2 3 7, 6, 5 4, 9, 15, 20, 27, 31, 36, 41, 47 18, 17, 16, 13, 12,11, 10 23, 22, 21 24 25
PIN NAME
VDD X1 X2
TYPE
PWR X2 Cr ystal Input X1 Cr ystal Output 3.3V power supply 14.318MHz Cr ystal input 14.318MHz Cr ystal output
DESCRIPTION
PCICLK_F (2:0)
GND PCICLK (6:0) 66MHz_OUT (2:0) 3V66 (4:2) 66MHz_IN 3V66_5 PD#
OUT
PWR OUT OUT OUT IN OUT IN
Free running PCI clock not affected by PCI_STOP# for power management.
Ground pins for 3.3V supply PCI clock outputs 66MHz buffered 66MHz_OUT from 66MHz_IN input. 66MHz reference clocks, from internal VCO 66MHz input to buffered 66MHz_OUT and PCI clocks 66MHz reference clock, from internal VCO Invokes power-down mode. Active Low.
28
Vtt_PWRGD#
IN I/O IN
OUT IN OUT OUT OUT IN OUT IN OUT OUT IN IN OUT
This 3.3V LVTTL input is a level sensitive strobe used to determine when FS[0:2] and MULTISEL0 inputs are valid and are ready to be sampled (active low) Data pin for I2C circuitry 5V tolerant Clock pin of I2C circuitry 5V tolerant
66MHz reference clocks, from internal VCO Halts PCICLK clocks at logic 0 level, when input low except PCICLK_F which are free running 3.3V output selectable through I2C to be 66MHz from internal VCO or 48MHz (non-SSC) 48MHz output clock for DOT 48MHz output clock for USB Special 3.3V input for Mode selection This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 3.3V LVTTL input for selecting the current multiplier for CPU outputs "Complementor y" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. Halts CPUCLK clocks at logic 0 level, when input low Frequency select pins 14.318MHz reference clock.
29 30 33 34 35 38 39 40 42 43 44, 48, 51 45, 49, 52 53 55, 54 56
SDATA SCLK 3V66_0 PCI_STOP# 3V66_1/VCH_CLK 48MHz_DOT 48MHz_USB FS2 I REF MULTSEL0 CPUCLKC (2:0) CPUCLKT (2:0) CPU_STOP# FS (1:0) REF
Power Groups
(Analog) VDDA = PLL1 VDD48 = 48MHz, PLL VDDREF = VDD for Xtal, POR (Digital) VDDPCI VDD3V66 VDDCPU
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Truth Table
FS2 0 0 0 0 1 1 1 1 Mid Mid Mid Mid FS1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 66.66 100.00 200.00 133.33 66.66 100.00 200.00 133.33 Tristate TCLK/2 3V66 (1:0) (MHz) 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 Tristate TCLK/4 66Buff (2:0) 3V66 (4:2) (MHz) 66.66 66.66 66.66 66.66 66MHz_IN 66MHz_IN 66MHz_IN 66MHz_IN Tristate TCLK/4 Reser ved Reser ved 66MHz_IN/ 3V66_5 66.66 66.66 66.66 66.66 Input Input Input Input Tristate TCLK/4 Reser ved Reser ved PCI_F PCI (MHz) 33.33 33.33 33.33 33.33 66MHz_IN/2 66MHz_IN/2 66MHz_IN/2 66MHz_IN/2 Tristate TCLK/8 Reser ved Reser ved REF0 (MHz) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 Tristate TCLK Reser ved Reser ved USB/DOT (MHz) 48.00 48.00 48.00 48.00 48.00 48.00 48.00 48.00 Tristate TCLK/2 Reser ved Reser ved
Reser ved Reser ved Reser ved Reser ved
Maximum Allowed Current
Condition Powerdown Mode (PWRDWN# = 0) Full Active Max 3.3V supply consumption Max discrete cap loads, Vdd = 3.465V All static inputs = Vdd or GND 40mA 360mA
Host Swing Select Functions
MULTISEL0 Board Target Trace/Term Z 50 ohms 50 ohms Reference R, Iref = VDD/(3*Rr) Rr = 221 1%, Iref = 5.00mA Rr = 475 1%, Iref = 2.32mA Output Current Ioh = 4* I REF Ioh = 6* I REF Voh @ Z
0 1
1.0V @ 50 0.7V @ 50
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ICS950805
Byte 0: Control Register
Bit Bit 0 Bit 1 Bit 2 Pin# 54 55 40 Name FS0 FS1 FS2 PWD2 X X X X Bit 3 34 PCI_STOP#
3
Type1 R R R R RW R RW
1 Bit 4 Bit 5 Bit 6 Bit 7 53 35 CPU_STOP# 3V66_1/VCH CPU_T(2:0) Spread Enabled X 0 0 0
RW
Description Reflects the value of FS0 pin sampled on power up Reflects the value of FS1 pin sampled on power up Reflects the value of FS2 pin sampled on power up Hardware mode: Reflects the value of PCI_STOP# pin sampled on PWD Software mode: 0=PCICLK stopped 1=PCICLK not stopped Reflects the current value of the external CPU_STOP# pin VCH Select 66MHz/48MHz 0=66MHz, 1=48MHz In power down mode controls output level 0=stop high 1=stop low 0=Spread Off, 1=Spread On
Byte 1: Control Register
Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Pin# 52, 51 49, 48 45, 44 52, 51 49, 48 45, 44 43 Name CPUCLKT0 CPUCLKC0 CPUCLKT1 CPUCLKC1 CPUCLKT2 CPUCLKC2 CPUCLKT0 CPUCLKC0 CPUCLKT1 CPUCLKC1 CPUCLKT2 CPUCLKC2 MULTSEL0 PWD2 1 1 1 0 0 0 0 X Type1 RW RW RW RW RW RW R Description 0=Disabled 1=Enabled4 0=Disabled 1=Enabled4 0=Disabled 1=Enabled4 Allow control of CPUCLKT0/C0 with asser tion of CPU_STOP# 0=Not free running 1=Free running Allow control of CPUCLKT1/C1 with asser tion of CPU_STOP# 0=Not free running 1=Free running Allow control of CPUCLKT2/C2 with asser tion of CPU_STOP# 0=Not free running 1=Free running (Reserved) Reflects the current value of MULTSEL0
Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default 3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP functionality via I2C Byte 0 Bit 3. In Hardware mode it is not allowed to write to the I2C Byte 0 Bit3. In Software mode it is not allowed to pull the external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it is not allowed to mix these modes. In Hardware mode the I2C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in PCI_STOP mode. Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I2C Byte 0 Bit 3 = 0)]. 4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high, CPUCLKC off, and external resistor termination will bring CPUCLKC low.
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ICS950805
Byte 2: Control Register
Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Pin# 10 11 12 13 16 17 18 -
Name PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 -
PWD 1 1 1 1 1 1 1 0
Type RW RW RW RW RW RW RW -
Description 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled (Reserved)
Byte 3: Control Register
Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Pin# 5 6 7 5 6 7 39 38 Name PCICLK_F0 PCICLK_F1 PCICLK_F2 PCICLK_F0 PCICLK_F1 PCICLK_F2 48MHz_USB 48MHz_DOT PWD 1 1 1 0 0 0 1 1 Type RW RW RW RW RW RW RW RW Description 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled Allow control of PCICLK_F0 with asser tion of PCI_STOP#. 0=Free Running, 1=Not free running Allow control of PCICLK_F1 with asser tion of PCI_STOP#. 0=Free Running, 1=Not free running Allow control of PCICLK_F2 with asser tion of PCI_STOP#. 0=Free Running, 1=Not free running 0=Disabled 1=Enabled 0=Disabled 1=Enabled
Byte 4: Control Register
Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Pin# 21 22 23 24 35 33 -
Name 66MHz_OUT0/3V66-2 66MHz_OUT0/3V66-3 66MHz_OUT0/3V66-4 3V66_5 3V66_1/VCH_CLK 3V66_0 -
PWD 1 1 1 1 1 1 0 0
Type RW RW RW RW RW RW R R
Description 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled (Reserved) (Reserved)
Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default
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ICS950805
Byte 5: Programming Edge Rate (1 = enable, 0 = disable)
Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bi t 7
Pin# X X X X X X X X
Name 48MHz_USB 48MHz_USB 48MHz_DOT 48MHz_DOT 66MHz_OUT[2:0] 66MHz_OUT[2:0] -
PWD 0 0 0 0 0 0 0 0
Type RW RW RW RW RW RW -
Description USB edge rate cntrol USB edge rate cntrol DOT edge rate control DOT edge rate control Tpd 66MHz_IN to 66MHz_OUT propagation delay control Tpd 66MHz_IN to 66MHz_OUT propagation delay control (Reserved) (Reserved)
Byte 6: Vendor ID Register (1 = enable, 0 = disable)
Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Pin# X X X X X X X X
Name Vendor ID Bit0 Vendor ID Bit1 Vendor ID Bit2 Vendor ID Bit3 Revision ID Bit0 Revision ID Bit1 Revision ID Bit2 Revision ID Bit3
PWD 1 1 1 1 1 1 1 1
Type R R R R R R R R
Description (Reserved) (Reserved) (Reserved) (Reserved) Revision ID values will be based on individual device's revision
Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default
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ICS950805
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +85C Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current I IL2 Operating Supply Current I DD3.3OP I DD3.3OP Powerdown Current Input Frequency Pin Inductance Input Capacitance1 Transition time Settling time1 Clk Stabilization1 Time to first clock 1 Delay 1
1 1
SYMBOL CONDITIONS MIN V IH 2 VSS-0.3 V IL VIN = VDD -5 I IH I IL1 VIN = 0 V; Inputs with no pull-up resistors -5 VIN = 0 V; Inputs with pull-up resistors CL = Full load; Select @ 100 MHz CL =Full load; Select @ 133 MHz IREF=5 mA VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins To 1st crossing of target frequency From 1st crossing to 1% target frequency From VDD = 3.3 V to 1% target frequency Time to first clock Output enable delay (all outputs) Output disable delay (all outputs) -200 229 220
TYP
MAX V DD+0.3 0.8 5
UNITS V V mA mA
230 233 38.1 14.318
360 360 45 7 5 6 45 3 3 3 1.8 10 10
mA mA mA MHz nH pF pF pF ms ms ms ms ns ns
I DD3.3PD Fi Lpin CIN COUT CINX Ttrans Ts TSTAB T1C t PZH,t PZL t PHZ,t PLZ
27
36
1 1 1
Guaranteed by design, not 100% tested in production.
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ICS950805
Electrical Characteristics - CPU
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Current Source Output Impedance Output High Voltage Output Low Voltage Rise Time Fall Time Duty Cycle Skew Jitter, Cycle to cycle
1 2
SYMBOL Zo1 V OH3 V OL3 tr3 tf3 dt3 tsk3 tjcyc-cyc
1
CONDITIONS VO = Vx IOH = -1 mA IOL = 1 mA VOL = 0.41V, VOH = 0.86V VOH = 0.86V V OL = 0.41V measurement from differential wavefrom 0.35V to +035V VT = 50% VT = 50%
MIN 3000 2.4 175 175 45
TYP
MAX UNITS W V
240 242 51 50 76
0.4 700 700 55 100 150
ps ps % ps ps
Guaranteed by design, not 100% tested in production. IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - PCICLK Buffered Mode
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter,cycle to cyc
1
SYMBOL FO1 VOH1 VOL1 IOH1 IOL1 t r11 t f11 dt11 tsk11 t jcyc-cyc
1
CONDITIONS
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 33
MAX 55 0.55 -33 38
UNITS MHz W V V mA mA ns ns % ps ps
RDSP11 VO = VDD*(0.5) I OH = -1 mA I OL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V (Additive)
1.29 1.32 51.9 209 60
0.5to 2 0.5 to 2 55 500 100
Guaranteed by design, not 100% tested in production.
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Electrical Characteristics - PCICLK Un-Buffered Mode
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter,cycle to cyc
1
SYMBOL FO1 RDSP11 VOH1 VOL1 IOH1 IOL1 tr11 tf11 dt11 tsk11 t jcyc-cyc
1
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 33
MAX 55 0.55 -33 38
UNITS MHz W V V mA mA ns ns % ps ps
1.32 1.39 52 247 111
0.5to 2 0.5 to 2 55 500 500
Guaranteed by design, not 100% tested in production.
Electrical Characteristics- 3V66 - Buffered Mode: 3V66 [1:0] 66MHz_OUT [2:0]
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter Skew Jitter
1
SYMBOL FO1 RDSP11 V OH1 V OL1 IOH1 IOL1 tr11 tf11 dt11 tsk1
1 1
CONDITIONS V O = V DD*(0.5) IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V V OL @MIN = 1.95 V, VOL @MAX = 0.4 V V OL = 0.4 V, V OH = 2.4 V V OH = 2.4 V, VOL = 0.4 V V T = 1.5 V V T = 1.5 V 3V66 [1:0] V T = 1.5 V 3V66 [1:0] (Additive) V T = 1.5 V 66MHz_OUT [2:0] V T = 1.5 V 66MHz_OUT [2:0]
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 66.66 33
MAX UNITS MHz 55 0.55 -33 38 W V V mA mA ns ns % ps ps ps ps
1.44 1.36 54.6 105 20 169 89
2 2 55 250 100 250 300
tjcyc-cyc tsk11 tjcyc-cyc
1
Guaranteed by design, not 100% tested in production.
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Electrical Characteristics - 3V66 -Un-Buffered Mode: 3V66 [5:0]
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL FO1 VOH1 VOL1 IOH1 IOL1 tr11 tf11 dt11 tsk1
1 1
CONDITIONS
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 66.66 33
MAX 55 0.55 -33 38
UNITS MHz W V V mA mA ns ns % ps ps
RDSP11 VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 3V66
1.38 1.45 54.4 243 139
2 2 55 500 300
tjcyc-cyc
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current 48DOT Rise Time 48DOT Fall Time VCH 48 USB Rise Time VCH 48 USB Fall Time 48 DOT Duty Cycle VCH 48 USB Duty Cycle 48 DOT Jitter VCH Jitter
1
SYMBOL FO1 RDSP11 V OH1 V OL1 IOH1 I OL1 t r11 t f11 t r11 t f11 dt11 dt11
1
CONDITIONS V O = VDD*(0.5) I OH = -1 mA I OL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V V OL @MIN = 1.95 V, V OL @MAX = 0.4 V V OL = 0.4 V, V OH = 2.4 V V OH = 2.4 V, VOL = 0.4 V V OL = 0.4 V, V OH = 2.4 V V OH = 2.4 V, VOL = 0.4 V V T = 1.5 V V T = 1.5 V
MIN 20 2.4 -29 29 0.5 0.5 1 1 45 45
TYP 48 48
MAX UNITS MHz 60 0.4 -23 27 W V V mA mA ns ns ns ns % % ps ps
0.6 0.8 1.2 1.3 52.8 53.5 183 223
1 1 2 2 55 55 350 350
t jcyc-cyc V T = 1.5 V t jcyc-cyc 1 V T = 1.5 V
Guaranteed by design, not 100% tested in production.
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ICS950805
Electrical Characteristics - REF
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL FO1 RDSP11 V OH1 V OL1 IOH1 IOL1 tr11 tf11 dt11 tjcyc-cyc
1
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, V OL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN 20 2.4 -29 29 1 1 45
TYP 48
MAX UNITS MHz 60 0.4 -23 27 W V V mA mA ns ns % ps
1.25 1.15 53 723
2 2 55 1000
Guaranteed by design, not 100% tested in production.
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ICS950805
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit ICS (Slave/Receiver)
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
* * * * * * * *
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS950805
Buffered Mode - 3V66[0:1], 66MHz_IN, 66MHz_OUT[0:2] and PCI Phase Relationship All 3V66 clocks are to be in phase with each other. All 66MHz_OUT clocks are to be in phase with each other. There is NO phase relationship between the 3V66 clocks and the 66MHz_OUT and PCI clocks. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci. The 66MHz_IN to 66MHz_OUT delay is shown in the figure below and is specified to be within a min and max propagation value.
66MHz_IN 66MHz_OUT
Tpd
Tpci PCICLK_F 3V66 No Relationship
Group Skews at Common Transition Edges: (Buffered Mode)
GROUP 3V66 66MHz_OUT PCI 66MHz_IN 66MHz_OUT 66MHz_OUT to PCI 66MHz_OUT1 to all CLK SYMBOL CONDITIONS 3V66 3V66 (1:0) pin to pin skew 66OUT 66MHz_OUT (2:0) pin to pin skew PCI Tpd Tpci Ts1 PCI_F (2:0) and PCI (6:0) pin to pin skew Propogation delay from 66MHz_IN to 66MHz_OUT (2:0) 66MHz_OUT (2:0) leads 33 MHz PCI MIN 0 0 0 2.5 1.5 30 150 TYP MAX UNITS 500 ps 175 ps 500 4.5 3.5 400 ps nS nS mS
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ICS950805
Un-Buffered Mode 3V66 & PCI Phase Relationship All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci.
3V66 (1:0) 3V66 (4:2) 3V66_5 PCICLK_F (2:0) PCICLK (6:0) Tpci
Group Skews at Common Transition Edges: (Un-Buffered Mode)
GROUP 3V66 PCI 3V66 to PCI
1
SYMBOL CONDITIONS 3V66 3V66 (5:0) pin to pin skew PCI S 3V66-PCI PCI_F (2:0) and PCI (6:0) pin to pin skew 3V66 (5:0) leads 33MHz PCI
MIN 0 0 1.5
TYP
MAX UNITS 500 ps 500 3.5 ps ns
Guarenteed by design, not 100% tested in production.
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ICS950805
Normal operation transition to Suspend State S1 Entry sequence of events:
1. Power-Down (PD#) pin is taken from a high to low to start into S1 Suspend state with digital filtering of the transition in the clock circuit. 2. The first clocks to be forced to a Stop Low power down condition are the PCI buffer output clocks after a full clock cycle. If the PCI_Stop# is low, then the free-running PCI clocks (for PCI and APIC signals) are the remaining PCI buffer clocks stopped. 3. Immediately after the PCI clocks have been stopped the 66Buf_0:2 clocks are stopped low after the next high to low transition. It will always be a sequence of PCI stopping, THEN the 66Buf clocks. 4. Following the two buffer output clocks being stopped (PCI then 66.6Buffer outputs), the remaining clocks within a short delay will transition to a stopped power-down state. The first of these driven clocks that transition to a stopped state are all of the CPU PLL clocks: the CPU and the driven 3V66 clocks. 5. After the CPU PLL clocks are stopped, the 48 MHz clocks (USB, DOT clocks) will stop low, then the REF clock 14.318 MHz clock will stop low. 6. After the clocks have all been stopped, the internal PLL stages and the Crystal oscillator will all be driven to a low power stopped condition. 7. As a note to power management calculations, please be aware that the CPU design requires that in the Power-Down (S1 mode) the CPU outputs have a differential bias voltage driving the differential input stage of the CPU in this S1 state. For this PD condition of the clock generator, the IDD_PD is running around 30 to 45 mA from having the Iref running (5 mA), the output multiplier bias generator at a 2X condition and the output current source outputs are running at a 2xIref bias level (for approx 10 mA each CPU output). This results in a higher level of Clock generator IDD_PD than in prior generations of clocks due to the CPU output differential requirements.
Suspend State S1 Exit transition to normal operation sequence of events:
1. Power-Down (PD#) pin is taken from Low to High with digital filtering of the transition in the clock circuit to return to normal running operation. 2. The Crystal Oscillator and the two PLL stages are released from PD to start-up to normal operation. No clocks will operate until the Lock detect circuitry verifies the PLL has reached stable final frequency (the same as normal initial power-up). 3. The CPU PLL clocks (differential CPU outputs and the driven 3V66_(0:1) clocks are operating first as soon as the Lock detect releases the clocks. With the release of these clocks, the single 66Buf_1 buffer driven output (at pin 22) is also released from the PD stopped state (but NOT the other 66Buf0,2 and not the PCI outputs). This allows the GMCH chipset 66.6 MHz DLL stage to start operating and have an operating feedback path before the other buffer outputs are released. This change is why the requirement is made that pin 22 be the connection from the clock to the GMCH chipset. Note that along with the 66Buf_0,2 and the PCI clocks, the 48 MHz and REF (14.318 MHz) clocks are also NOT released at this point. 4. A delay is built into the clock generator that allows the CPU, driven 3V66_0,1 and the single buffer clock 66Buf_1 (at pin 22) to operate before other clocks are released. This delay is larger than 30 uS and shorter than 400 uS, and after this the other clocks are staged for a sequential release. 5. The initial clocks released after the delay are the 66Buf_0, 2 outputs. 6. After the 66Buf_0,2 clocks are released, then the PCI clocks are released. 7. It will always be the sequence of 66_1 (pin 22) released with the CPU clocks, then after the delay the remaining 66Buf_0,2 first, THEN the PCI clocks. 8. Following the 66Buf_0,2 clocks, the 48 MHz (DOT and USB clocks) and the REF (14.318MHz) clocks are released. 9. Note, the initial power-up time is the same as this PD release, the PLL will power-up and the outputs will be running within a 3 ms time point.
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ICS950805
PCI_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP# PCI_F[2:0] 33MHz PCI[6:0] 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven. Assertion of CPU_STOP# Waveforms
CPU_STOP# CPUT CPUC
CPU_STOP# Functionality
CPU_STOP# 1 0
CPUT Normal iref * Mult
CPUC Normal Float
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ICS950805
PD# - Assertion (transition from logic "1" to logic "0") When PD# is sampled low by two consecutive rising edges of CPU clock then all clock outputs except CPU clocks must be held low on their next high to low transition. CPU clocks must be held with the CPU clock pin driven high with a value of 2x Iref, and CPUC undriven. Note the example below shows CPU = 100MHz, this diagram and description is applicable for all valid CPU frequencies 66, 100, 133, 200MHz. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Power Down Assertion of Waveforms - Buffered Mode
0ns PD# CPUT 100MHz CPUC 100MHz 3V66MHz 66MHz_IN 66MHz_OUT PCI 33MHz USB 48MHz REF 14.318MHz 25ns 50ns
PD# Functionality
CPU_STOP# 1 0
CPUT Normal iref * Mult
CPUC Normal Float
3V66 66MHz Low
66MHz_OUT 66MHz_IN Low
PCICLK_F PCICLK 66MHz_IN Low
PCICLK 66MHz_IN Low
USB/DOT 48MHz 48MHz Low
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ICS950805
N
c
SYMBOL
L
INDEX AREA
E1
E
12 D h x 45
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 18.31 18.55
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 56
10-0034
D (inch) MIN .720 MAX .730
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS950805yF-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type Prefix ICS, AV = Standard Device
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ICS950805
N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 56
10-0039
-Ce
b SEATING PLANE
D mm. MIN 13.90 MAX 14.10 MIN .547
D (inch) MAX .555
aaa C
Reference Doc.: JEDEC Publication 95, MO-153
(240 mil)
6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil)
Ordering Information
ICS950805yG-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type Prefix ICS, AV = Standard Device
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